1. Field of the Invention
The present invention relates to a microprocessor, and more particularly, to a microprocessor which improves economical efficiency of a device.
2. Discussion of the Related Art
Generally, a microprocessor receives a virtual address which is used in a memory management unit (MMU) having a pace size of 4 KB and in which low 12 bits are identical with a physical address and high 20 bits are different from the physical address, and inspects cache tags per cycle to determined hit/miss of a cache, so that it takes much power consumption and much time. Actually, a static random access memory (SRAM) occupies about 60% of total power consumption.
A background art MMU and cache will be described with reference to FIG. 1.
The MMU includes a virtual address of 32 bits in which low 12 bits are identical with a physical address and high 20 bits are different from the physical address, a first latch 11 which reserves the virtual address, a translation look-aside buffer (TLB) 12 for receiving high 20 bits of the virtual address from the first latch 11, a TLB miss handler 13 for mutually inputting/outputting data with the TLB 12, and a multiplexer 14 for receiving the output of the TLB 12 or the TLB miss handler 13.
The cache includes four tag RAMs 15 for receiving low 12 bits of the virtual address, a first comparator 16 for comparing 20 bits of the tag RAMs selected by low 12 bits of the virtual address with 20 bits of the multiplexer 14, a cache miss handler 17 for receiving the outputs of the multiplexer 14 and the first comparator 16, four data RAMs 18 for receiving the output of the tag RAMs 15, and a data latch 19 for storing and outputting data corresponding to the output of the tag RAMs 15, which is identical with 20 bits of the multiplexer 14.
As shown in FIG. 2, the TLB 12 includes eight least recently useds (LRU) 20 of 3 bits, tags 21 of 20 bits having the same number as the LRUs 20, attributes 22 having the same number as the tags 21, for indicating attribute of each of the tags 21, i.e., whether each of the tags 21 is valid, modified, or up-graded, physical pages 23 of 20 bits having the same number as the tags 21, a second comparator 24 for comparing 20 bits of the tags 21 with high 20 bits of the virtual address, and an attribute checker 25.
The data of the virtual address are selected or erased based on the LRUs 20 when inputting data of a new virtual address to the tags 21 at the state that data of the virtual address are input to all the tags 21.
The operation of the background art MMU and cache will be described below.
The virtual address of 32 bits in which low 12 bits are identical with the physical address and high 20 bits are different from the physical address is input to the first latch 11. Then, the low 12 bits of the virtual address are output to the tag RAMs 15 and its high 20 bits are output to the TLB 12. At this time, the tag RAMs 15 select four data whose low 12 bits are identical with the low 12 bits of the virtual address.
Subsequently, the TLB 12 compares 20 bits of each of the tags 21 with the high 20 bits of the virtual address. As a results, the TLB 12 determines a hit if there are the same tags 21 as the high 20 bit of the virtual address. If not, the TLB 12 determines a miss.
First, if a hit is determined by the TLB 12, that is, if there are the same tags 21 as the high 20 bits of the virtual address, 20 bits data of the physical pages 23 corresponding to the tags 21 are output to the multiplexer 14.
At this time, the multiplexer 14 outputs the output of the TLB 12, i.e., the 20 bit data of the physical pages 23 to the first comparator 16. The first comparator 16 compares the 20 bit data of the physical pages 23 with each data selected by the four tag RAMs 15. As a result, if there are the same data as those of the physical pages 23 in tag RAMs 15, the data RAMs 18 receive the output of the tag RAMs 15 to detect one data which is identical with the data of the tag RAMs and outputs the detected data outside through the data latch 19. On the other hand, if there are no data the same as those of the physical pages 23 in the tag RAMs 15, the first comparator 16 outputs a miss to the cache miss handler 17.
The cache miss handler 17 outputs data corresponding to the physical pages 23, i.e., the output of the TLB 12 missed by the tag RAMs 15 outside from a memory (not shown) of the microprocessor and at the same time stores the same in the tag RAMs 15 and the data RAMs 18.
Further, if a miss is determined by the TLB 12, that is, if there are no tags 21 the same as the high 20 bits of the virtual address, the TLB 12 outputs a miss to the TLB miss handler 13.
The TLB miss handler 13 produces the tags 21 and the physical pages 23 corresponding to the high 20 bits of the virtual address missed by the TLB 12, outputs the 20 bits data of the physical pages 23 corresponding to the tag 21 of the new data to the multiplexer 14 and at the same time stores the produced tag 21 and the physical pages 23 in the TLB 12. Thereafter, the same operation as a hit is performed.
Therefore, the first comparator 16 uses all 20 bits data of the physical pages 23 to inspect the tag RAMs 15. This results in that the four tag RAMs 15 are compared 20 bits.times.4 [four tag RAMs], i.e. 80 times.
The background art microprocessor has several problems.
Since the tag RAMs are compared using all 20 bits of the physical pages, total 80 times are compared to determine hit/miss. This requires a circuit having fast comparing speed and increases power consumption, thereby reducing economical efficiency.